In high-end computing systems such as servers and workstations, there is necessarily a strong focus on stability and performance, especially with regards to high speed interfaces. In this regard, hardware and software elements are finely tuned to obtain the largest possible eye margin, the eye margin being amount of time measured between the setup time (time that data is required to remain stable prior to sampling) of the signal to the hold time (time that the data is required to remain stable subsequent to sampling) of the same signal.
In operation, larger signal eyes correspond to a larger margin, and thus greater operational stability. A larger eye allows the signal to be sampled more reliably and makes the interface more resilient to errors, such as cross talk interference, inter-symbol interference, and power fluctuations that might occur during operation.
In interface training, high speed interconnects are able to programmatically control the phase relationship between the sampling “strobe” and the signal to be sampled to adjust the phase relationship. The control over the phase relationship may be implemented using various circuit implementations to create delay stages within the IO (Input Output) circuit. In certain cases, both the signal and the sampling strobe must be delayed in the interface training process.
However, when a phase delay is applied to the actual signal (in addition to the sampling strobe) via enablement of additional delay stage circuitry, there are consequences of increased power and latency in operation. This increase in latency creates a negative impact on performance of the system.